1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to gate dielectric layers formed on integrated circuit devices.
2. Description of the Related Art
As the size of semiconductor device is scaled down, the requirements for device design and fabrication—such as controlling the thickness of thin gate dielectric and other constituent layers and/or obtaining desired dielectric film composition—continue to be tightened. In addition, scaled down conventional bulk silicon MOSFET devices tend to have diminished gain in drive currents while having increased adverse short channel effects. Double gate Fully Depleted Semiconductor-on-Insulator (FDSOI) technology has been established as one solution to reduce short channel effect as well as to improve drive current (high transconductance). In addition, double gate FDSOI technology may require a less stringent requirement on the thickness of a semiconductor on insulator, and may reduce the Drain Induced Virtual Substrate Biasing (DIVSB) effect. However, it has been difficult to build a simple, manufacturable planar double gate FDSOI transistor structure that can be used to fabricate transistors in differing applications.
Accordingly, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.